The present invention relates to a voltage reference stabilization circuit for supplying a reference voltage at a reference node and, more particularly, to a circuit for stabilizing this reference voltage.
Voltage references are used in analog type MOS circuitry to bias the circuits at a given operating point. Voltage references are commonly used with sense amplifiers and high impedance loads. Typically, voltage reference generation is accomplished through a voltage divider network. The reference voltage is then taken off a node of the voltage divider.
In CMOS circuits that have voltage referenced analog circuitry, the dc current path of the reference must be shut off when the part is in standby mode. Disabling the current path through the voltage divider allows the reference node to pull to VCC or VSS, or will tri-state the reference node.
However, a problem arises with this gating technique. When the reference is first enabled, the reference node must be pulled from VCC or VSS (or somewhere in between) to the normal reference voltage. The amount of time required for the reference node to be pulled to its normal reference level and stabilized at this level can be considerable, especially if the reference node is heavily loaded. Since in CMOS memory applications, the circuitry which uses the reference voltage partially determines the overall speed of the device, it is important to establish and stabilize a reference voltage as quickly as possible. In any event, the reference voltage must be established and stabilized before the circuitry using the reference voltage can be utilized. Thus, reducing the stabilization time will increase the overall speed of the device.
Therefore, an object of the invention is to provide a circuit which will stabilize the reference node near its normal operating point when the reference is disabled.
Another object of the invention is to provide a voltage reference stabilization circuit which improves the overall speed of the memory device by reducing the time required for the reference node to be pulled to its normal reference level.
A further object of the invention is to provide a voltage reference stabilization circuit which ensures that the circuitry which uses the reference voltage will function properly, by establishing the proper reference voltage before the circuitry is utilized.
These and other objects are obtained in the present invention by providing a voltage reference stabilization circuit having a reference voltage generator for supplying a reference voltage at a reference node. The reference voltage generator is enabled and disabled by enable circuit, while a clamping circuit clamps the reference node at a clamp voltage approximately equal to the reference voltage whenever the reference voltage generator is disabled by the enable means.
An advantage of the voltage reference stabilization circuit provided by the present invention is the elimination of a large part of the delay in establishing a reference voltage. By substantially eliminating the delay, the proper functioning and the speed performance of the analog circuitry that uses the voltage reference is increased. This increases the overall speed of the memory device.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.